//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : over sample the input data with 8-phases 311M clock
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths

module LINF_TX(
   input                         LINF_RESET,

   input                         GTM_SYSCLK311,
   input                         GTM_SYSCLK155,
   input                         GTM_SYSCLK77,

   input[7:0]                    LINF_TXD,
   output                        AFE_TXD
   );



reg[63:0]                        TBUF_REGS;
reg[2:0]                         TBUF_WRCNT;

reg[3:0]                         TBUF_RDCNT;
reg[3:0]                         TBUF_RD;

reg                              TMUX_CPEN4;
reg[3:0]                         TMUX_DATA4;
reg[1:0]                         TMUX_DATA2;
reg                              TMUX_DATA_LO;


always @( posedge LINF_RESET or posedge GTM_SYSCLK77) begin
   if ( LINF_RESET==1'b1 )
      TBUF_WRCNT[2:0]                              <= 3'd0;
   else
      TBUF_WRCNT[2:0]                              <= TBUF_WRCNT[2:0] +3'd1;
end

always @( posedge LINF_RESET or posedge GTM_SYSCLK77) begin
   if ( LINF_RESET==1'b1 )
      TBUF_REGS[63:0]                              <= 64'd0;
   else begin
      case (TBUF_WRCNT[2:0])
      3'b000 :  TBUF_REGS[7:0]                     <= LINF_TXD[7:0];
      3'b001 :  TBUF_REGS[15:8]                    <= LINF_TXD[7:0];
      3'b010 :  TBUF_REGS[23:16]                   <= LINF_TXD[7:0];
      3'b011 :  TBUF_REGS[31:24]                   <= LINF_TXD[7:0];
      3'b100 :  TBUF_REGS[39:32]                   <= LINF_TXD[7:0];
      3'b101 :  TBUF_REGS[47:40]                   <= LINF_TXD[7:0];
      3'b110 :  TBUF_REGS[55:48]                   <= LINF_TXD[7:0];
      3'b111 :  TBUF_REGS[63:56]                   <= LINF_TXD[7:0];
      default: ;
      endcase
   end
end

always @( posedge LINF_RESET or posedge GTM_SYSCLK155) begin
   if ( LINF_RESET==1'b1 )
      TBUF_RDCNT[3:0]                              <= 4'd8;
   else
      TBUF_RDCNT[3:0]                              <= TBUF_RDCNT[3:0] +4'd1;
end

always @( posedge LINF_RESET or posedge GTM_SYSCLK155) begin
   if ( LINF_RESET==1'b1 )
      TBUF_RD[3:0]                                 <= 4'd0;
   else begin
      case ( TBUF_RDCNT[3:0] )
      4'h0 : TBUF_RD[3:0]                          <= TBUF_REGS[7:4];
      4'h1 : TBUF_RD[3:0]                          <= TBUF_REGS[3:0];
      4'h2 : TBUF_RD[3:0]                          <= TBUF_REGS[15:12];
      4'h3 : TBUF_RD[3:0]                          <= TBUF_REGS[11:8];
      4'h4 : TBUF_RD[3:0]                          <= TBUF_REGS[23:20];
      4'h5 : TBUF_RD[3:0]                          <= TBUF_REGS[19:16];
      4'h6 : TBUF_RD[3:0]                          <= TBUF_REGS[31:28];
      4'h7 : TBUF_RD[3:0]                          <= TBUF_REGS[27:24];
      4'h8 : TBUF_RD[3:0]                          <= TBUF_REGS[39:36];
      4'h9 : TBUF_RD[3:0]                          <= TBUF_REGS[35:32];
      4'hA : TBUF_RD[3:0]                          <= TBUF_REGS[47:44];
      4'hB : TBUF_RD[3:0]                          <= TBUF_REGS[43:40];
      4'hC : TBUF_RD[3:0]                          <= TBUF_REGS[55:52];
      4'hD : TBUF_RD[3:0]                          <= TBUF_REGS[51:48];
      4'hE : TBUF_RD[3:0]                          <= TBUF_REGS[63:60];
      4'hF : TBUF_RD[3:0]                          <= TBUF_REGS[59:56];
      default:;
      endcase
   end
end

always @( posedge LINF_RESET or posedge GTM_SYSCLK311) begin
   if ( LINF_RESET==1'b1 )
      TMUX_CPEN4                                   <= 1'b0;
   else
      TMUX_CPEN4                                   <= !TMUX_CPEN4;
end

always @( posedge LINF_RESET or posedge GTM_SYSCLK311) begin
   if ( LINF_RESET==1'b1 )
      TMUX_DATA4[3:0]                              <= 4'd0;
   else if ( TMUX_CPEN4==1'b1 )
      TMUX_DATA4[3:0]                              <= TBUF_RD[3:0];
end

always @( posedge LINF_RESET or posedge GTM_SYSCLK311) begin
   if ( LINF_RESET==1'b1 )
      TMUX_DATA2[1:0]                              <= 2'd0;
   else begin
      if ( TMUX_CPEN4==1'b0 )
         TMUX_DATA2[1:0]                           <= TMUX_DATA4[3:2];
      else
         TMUX_DATA2[1:0]                           <= TMUX_DATA4[1:0];
   end
end
always @( posedge LINF_RESET or negedge GTM_SYSCLK311) begin
   if ( LINF_RESET==1'b1 )
      TMUX_DATA_LO                                 <= 1'b0;
   else
      TMUX_DATA_LO                                 <= TMUX_DATA2[0];
end

LVDSDDRO                                AFE_DDR(
   .datain_h                           ( TMUX_DATA2[1] ),
   .datain_l                           ( TMUX_DATA_LO ),
   .outclock                           ( GTM_SYSCLK311 ),
   .dataout                            ( AFE_TXD )
   );

endmodule


